spread spectrum bx system frequency generator w48c101-01 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-07192 rev. *a revised december 22, 2002 01-01 features ? maximized emi suppression using cypress?s spread spectrum technology four copies of cpu output eight copies of pci output (synchronous w/cpu output) two copies of 14.318-mhz ioapic output two copies of 48-mhz usb output three buffered copies of 14.318-mhz reference input input is a 14.318-mhz xtal or reference signal selectable 100-mhz or 66-mhz cpu outputs power management control input pins test mode and output three-state capability key specifications supply voltages: ....................................... v ddq3 = 3.3v5% v ddq2 = 2.5v5% or 3.3v5% cpu0:3 jitter (cycle to cycle): ................................... 200 ps cpu0:3 clock skew: ...................................................175 ps pci_f, pci1:7 clock skew: .........................................500 ps cpu to pci clock skew: .............. 1.5 to 4.0 ns (cpu leads) logic inputs have 250-k ? pull-up resistors except sel100/66#. table 1. pin selectable frequency sel 100/66# sel1 sel0 cpu (mhz) pci (mhz) spread#=0 0 0 0 hi-z hi-z don ? t care 0 0 1 66.6 33.3 0.9% center 0 1 0 66.6 33.3 ? 1% down 0 1 1 66.6 33.3 ? 0.5% down 1 0 0 x1/2 x1/6 don ? t care 1 0 1 100 33.3 0.9% center 1 1 0 100 33.3 ? 1% down 1 1 1 100 33.3 ? 0.5% down pin configuration block diagram ref0 ref1 gnd x1 x2 gnd pci_f pci1 vddq3 pci2 pci3 gnd pci4 pci5 vddq3 pci6 pci7 gnd vddq3 gnd vddq3 48mhz 48mhz gnd vddq3 ref2 vddq2 apic0 apic1 gnd nc vddq2 cpu0 cpu1 gnd vddq2 cpu2 cpu3 gnd vddq3 gnd pci_stop# cpu_stop# pwr_dwn# spread# sel0 sel1 sel100/66# 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 vddq3 ref0 vddq2 apic0 cpu0 cpu1 cpu2 cpu3 pci_f xtal pll ref freq pll 1 sel100/66# x2 x1 ref1 vddq3 stop clock control stop clock control pci1 pwr_dwn# power down control pci2 pci3 pci4 pci5 48mhz 48mhz pll2 2/ 3 osc ref2 vddq2 pci_stop# cpu_stop# pci6 pci7 vddq3 apic1 sel0 sel1 spread#
w48c101-01 document #: 38-07192 rev. *a page 2 of 9 pin definitions pin name pin no. pin type pin description cpu0:3 40, 39, 36, 35 o cpu clock outputs 0 through 3: these four cpu clock outputs are controlled by the cpu_stop# control pin. output voltage swing is controlled by voltage applied to vddq2. pci1:7 8, 10, 11, 13, 14, 16, 17 o pci bus clock outputs 1 through 7: these seven pci clock outputs are con- trolled by the pci_stop# control pin. output voltage swing is controlled by voltage applied to vddq3. pci_f 7 o fixed pci clock output: unlike pci1:7 outputs, this output is not controlled by the pci_stop# control pin. output voltage swing is controlled by voltage applied to vddq3. cpu_stop# 30 i cpu_stop# input: when brought low, clock outputs cpu0:3 are stopped low after completing a full clock cycle (2 ? 3 cpu clock latency). when brought high, clock outputs cpu0:3 start beginning with a full clock cycle (2 ? 3 cpu clock latency). pci_stop# 31 i pci_stop# input: the pci_stop# input enables the pci 1:7 outputs when high and causes them to remain at logic 0 when low. the pci_stop signal is latched on the rising edge of pci_f. its effects take place on the next pci_f clock cycle. spread# 28 i spread# input: when brought low this pin activates spread spectrum clocking. apic0:1 45, 44 o i/o apic clock outputs: provides 14.318-mhz fixed frequency. the output volt- age swing is controlled by vddq2. 48mhz 22, 23 o 48-mhz outputs: fixed clock outputs at 48 mhz. output voltage swing is controlled by voltage applied to vddq3. ref0:2 1, 2, 47 o fixed 14.318-mhz outputs 0 through 2: used for various system applications. output voltage swing is controlled by voltage applied to vddq3. sel100/66# sel1:0 25, 26, 27 i frequency selection input: selects power-up default cpu clock frequency as shown in table 1 on page 1. x1 4 i crystal connection or external reference frequency input: connect to either a 14.318-mhz crystal or reference signal. x2 5 i crystal connection: an input connection for an external 14.318-mhz crystal. if using an external reference, this pin must be left unconnected. pwr_dwn# 29 i power down control: when this input is low, device goes into a low-power condition. all outputs are held low while in power-down. cpu and pci clock out- puts are stopped low after completing a full clock cycle (2 ? 3 cpu clock cycle latency). when brought high, cpu, sdram and pci outputs start with a full clock cycle at full operating frequency (3 ms maximum latency). vddq3 9, 15, 19, 21, 33, 48 p power connection: connect to 3.3v supply. vddq2 37,41,46 p power connection: power supply for cpu0:3 and apic0:1 output buffers. con- nect to 2.5v supply or 3.3v supply. gnd 3, 6, 12, 18, 20, 24, 32, 34, 38, 43 g ground connection: connect all ground pins to the common system ground plane. nc 42 - no connect: do not connect.
w48c101-01 document #: 38-07192 rev. *a page 3 of 9 spread spectrum clocking the device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. by increasing the bandwidth of the fundamental and its harmonics, the am- plitudes of the radiated electromagnetic emissions are re- duced. this effect is depicted in figure 1 . as shown in figure 1 , a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. the reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. the equation for the reduction is: db = 6.5 + 9*log 10 (p) + 9*log 10 (f) where p is the percentage of deviation and f is the frequency in mhz where the reduction is measured. the output clock is modulated with a waveform depicted in figure 2 . this waveform, as discussed in ? spread spectrum clock generation for the reduction of radiated emissions ? by bush, fessler, and hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. the deviation selected for this chip is ? 0.5%, ? 1.0%, or 0.9% of the selected frequency. figure 2 details the cypress spreading pattern. cypress does offer options with more spread and greater emi reduction. contact your local sales representative for details on these devices. spread spectrum clocking is activated or deactivated by se- lecting the appropriate values for spread#. figure 1. clock harmonic with and without sscg modulation frequency domain representation ? ssc non- ssc highest of f nom f nom max (+0.5%) min ( ? 0.5%) 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% frequency figure 2. typical modulation profile
w48c101-01 document #: 38-07192 rev. *a page 4 of 9 absolute maximum ratings [1] stresses greater than those listed in this table may cause per- manent damage to the device. these represent a stress rating only. operation of the device at these or any other conditions above those specified in the operating sections of this specifi- cation is not implied. maximum conditions for extended peri- ods may affect reliability. parameter description rating unit v dd , v in voltage on any pin with respect to gnd ? 0.5 to +7.0 v t stg storage temperature ? 65 to +150 c t a operating temperature 0 to +70 c t b ambient temperature under bias ? 55 to +125 c esd prot input esd protection 2 (min.) kv dc electrical characteristics: t a = 0 c to +70 c, v ddq3 = 3.3v5%, v ddq2 = 2.5v5% parameter description test condition min. typ. max. unit supply current i ddq3 3.3v supply current cpu0:3 = 100 mhz outputs loaded [2] 120 ma i ddq2 2.5v supply current cpu0:3 = 100 mhz outputs loaded [2] 65 ma logic inputs v il input low voltage gnd ? 0.3 0.8 v v ih input high voltage 2.0 v dd + 0.3 v i il input low current [3] ? 25 a i ih input high current [3] 10 a i il input low current (sel100/66#) ? 5a i ih input high current (sel100/66#) 5 a clock outputs v ol output low voltage i ol = 1 ma 50 mv v oh output high voltage i oh = ? 1 ma 3.1 v v oh output high voltage cpu0:3, apic0:1 i oh = ? 1 ma 2.2 v i ol output low current cpu0:3 v ol = 1.25v 45 65 100 ma pci_f, pci1:7 v ol = 1.5v 70 100 145 ma apic0:1 v ol = 1.25v 60 90 140 ma ref0:2 v ol = 1.5v 45 65 100 ma 48mhz v ol = 1.5v 45 65 100 ma i oh output high current cpu0:3 v ol = 1.25v 45 65 100 ma pci_f, pci1:7 v ol = 1.5v 65 95 135 ma apic0:1 v ol = 1.25v 55 80 115 ma ref0:2 v ol = 1.5v 45 65 100 ma 48mhz v ol = 1.5v 45 65 100 ma notes: 1. multiple supplies: the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing i s not required. 2. all clock outputs loaded with 6" 60 ? transmission lines with 20-pf capacitors. 3. w48c101-01 logic inputs have internal pull-up devices, except sel100/66# (pull-ups not full cmos level).
w48c101-01 document #: 38-07192 rev. *a page 5 of 9 ac electrical characteristics t a = 0 c to +70 c, v ddq3 = 3.3v5%,v ddq2 = 2.5v 5%, f xtl = 14.31818 mhz ac clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output; spread spectrum clocking is disabled. crystal oscillator v th x1 input threshold voltage [4] 1.65 v c load load capacitance, as seen by external crystal [5] 14 pf c in,x1 x1 input capacitance [6] pin x2 unconnected 28 pf pin capacitance/inductance c in input pin capacitance except x1 and x2 5 pf c out output pin capacitance 6pf l in input pin inductance 7nh dc electrical characteristics: t a = 0 c to +70 c, v ddq3 = 3.3v5%, v ddq2 = 2.5v5% (continued) parameter description test condition min. typ. max. unit cpu clock outputs, cpu0:3 (lump capacitance test load = 20 pf) parameter description test condition/comments cpu = 66.6 mhz cpu = 100 mhz unit min. typ. max. min. typ. max. t p period measured on rising edge at 1.25v 15 15.5 10 10.5 ns t h high time duration of clock cycle above 2.0v 5.2 3.0 ns t l low time duration of clock cycle below 0.4v 5.0 2.8 ns t r output rise edge rate measured from 0.4v to 2.0v 1 4 1 4 v/ns t f output fall edge rate measured from 2.0v to 0.4v 1 4 1 4 v/ns t d duty cycle measured on rising and falling edge at 1.25v 45 55 45 55 % t jc jitter, cycle-to-cycle measured on rising edge at 1.25v. max- imum difference of cycle time between two adjacent cycles. 200 200 ps t sk output skew measured on rising edge at 1.25v 175 175 ps f st frequency stabiliza- tion from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 33ms z o ac output impedance average value during switching transi- tion. used for determining series termi- nation value. 20 20 ? notes: 4. x1 input threshold voltage (typical) is v dd /2. 5. the w48c101-01 contains an internal crystal load capacitor between pin x1 and ground and another between pin x2 and ground. t otal load placed on crystal is 14 pf; this includes typical stray capacitance of short pcb traces to crystal. 6. x1 input capacitance is applicable when driving x1 with an external clock source (x2 is left unconnected).
w48c101-01 document #: 38-07192 rev. *a page 6 of 9 pci clock outputs, pci1:7 and pci_f (lump capacitance test load = 30 pf parameter description test condition/comments cpu = 66.6/100 mhz unit min. typ. max. t p period measured on rising edge at 1.5v 30 ns t h high time duration of clock cycle above 2.4v 12 ns t l low time duration of clock cycle below 0.4v 12 ns t r output rise edge rate measured from 0.4v to 2.4v 1 4 v/ns t f output fall edge rate measured from 2.4v to 0.4v 1 4 v/ns t d duty cycle measured on rising and falling edge at 1.5v 45 55 % t jc jitter, cycle-to-cycle measured on rising edge at 1.5v. maximum difference of cycle time between two adjacent cycles. 250 ps t sk output skew measured on rising edge at 1.5v 500 ps t o cpu to pci clock skew covers all cpu/pci outputs. measured on rising edge at 1.5v. cpu leads pci output. 1.5 4 ns f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 3ms z o ac output impedance average value during switching transition. used for determining series termination value. 15 ? apic0:1 clock outputs (lump capacitance test load = 20 pf) parameter description test condition/comments cpu = 66.6/100mhz unit min. typ. max. f frequency, actual frequency generated by crystal oscillator 14.31818 mhz t r output rise edge rate measured from 0.4v to 2.0v 1 4 v/ns t f output fall edge rate measured from 2.0v to 0.4v 1 4 v/ns t d duty cycle measured on rising and falling edge at 1.25v 45 55 % f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 1.5 ms z o ac output impedance average value during switching transition. used for determining series termination value. 15 ? ref0:2 clock outputs (lump capacitance test load = 20 pf) parameter description test condition/comments cpu = 66.6/100 mhz unit min. typ. max. f frequency, actual frequency generated by crystal oscillator 14.318 mhz t r output rise edge rate measured from 0.4v to 2.4v 0.5 2 v/ns t f output fall edge rate measured from 2.4v to 0.4v 0.5 2 v/ns t d duty cycle measured on rising and falling edge at 1.5v 45 55 % f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 3ms z o ac output impedance average value during switching transition. used for determining series termination value. 25 ?
w48c101-01 document #: 38-07192 rev. *a page 7 of 9 48-mhz clock outputs (lump capacitance test load = 20 pf = 66.6/100 mhz) parameter description test condition/comments cpu = 66.6/100 mhz unit min. typ. max. f frequency, actual determined by pll divider ratio (see m/n below) 48.008 mhz f d deviation from 48 mhz (48.008 ? 48)/48 +167 ppm m/n pll ratio (14.31818 mhz x 57/17 = 48.008 mhz) 57/17 t r output rise edge rate measured from 0.4v to 2.4v 1 4 v/ns t f output fall edge rate measured from 2.4v to 0.4v 1 4 v/ns t d duty cycle measured on rising and falling edge at 1.5v 45 55 % f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to fre- quency stabilization. 3ms z o ac output impedance average value during switching transition. used for determining series termination value. 25 ? ordering information ordering code freq. mask code package name package type w48c101 -01 h 48-pin ssop (300 mils)
w48c101-01 document #: 38-07192 rev. *a page 8 of 9 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagram 48-pin small shrink outline package (ssop, 300 mils) summary of nominal dimensions in inches: body width: 0.296 lead pitch: 0.025 body length: 0.625 body height: 0.102
w48c101-01 document #: 38-07192 rev. *a page 9 of 9 document title: w48c101-01 spread spectrum bx system frequency generator document number: 38-07192 rev. ecn no. issue date orig. of change description of change ** 110593 12/15/01 dsg change from spec number: 38-00852 to 38-07192 *a 12823 12/22/02 rbi add power up requirements to maximum ratings information
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